A single memory cell of a dynamic random-access memory comprises an access transistor and a capacitor that retains an electrical charge representing a data bit. Partly because the access transistor of such a cell is not a perfect insulator, an electric charge residing in the capacitor leaks out over the course of time. Because of this leakage, barring any change of state required in the bit-state, the charge representing a bit must be replenished periodically.
A single instance of recharging the capacitors for a row of DRAM cells is called in the art a refresh cycle. A refresh cycle is basically a read cycle without data transfer to the memory I/O port.
Various schemes are employed in current art to compensate for the time required for a refresh cycle, but there are no refresh protocols that do not depend at least to some extent on time that might be otherwise profitably used by a computer.
A refresh cycle starts with a read operation during which electric charges stored in memory cells of an addressed row are sensed and amplified. The amplified charges are then returned to the memory cells to replenish (refresh) the charges in the memory cells. Every page read or refresh action is immediately followed by a precharge operation during which the electric potential of all bit lines is returned to about one-half the memory supply voltage. Whatever is done to limit the time required for a refresh, the recharge time is non-productive and contributes to the length of the overall refresh cycle. Consequently, precharge time retards the rate at which data may be stored and retrieved from DRAM.
Steady advances have been achieved in computer performance by many inventive methods and apparatus. Still, developers are aware that like improvements must be made in CPUs as in memory performance to achieve even better performance. Unfortunately, memory speed, and in particular DRAM speed, has not increased at the same rate as microprocessor speed.
What is clearly needed is a method to improve DRAM speed by reducing the time needed for precharge operations.